Formal Verifications in Modern Chip Designs

Summary form only given. Formal technologies have matured rapidly in recently years to become an indispensable technology powering many practical and production-proven formal verification solutions. In this presentation, we survey how formal technologies have enabled logic equivalence checking, desi...

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Main Author: Kei-Yong Khoo
Format: Conference Proceeding
Language:English
Subjects:
Chip scale packaging
Conferences
Formal verification
Logic design
Power system management
System testing
Technology management
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description Summary form only given. Formal technologies have matured rapidly in recently years to become an indispensable technology powering many practical and production-proven formal verification solutions. In this presentation, we survey how formal technologies have enabled logic equivalence checking, design-constraint management, and low-power design verifications. In addition, we examine modern and emerging design styles and techniques, and requirements on formal technologies to meet the new verification challenges
doi_str_mv 10.1109/HLDVT.2006.320001
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identifier ISSN: 1552-6674
ispartof 2006 IEEE International High Level Design Validation and Test Workshop, 2006, p.38-38
issn 1552-6674
2471-7827
language eng
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Chip scale packaging
Conferences
Formal verification
Logic design
Power system management
System testing
Technology management
title Formal Verifications in Modern Chip Designs
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