A Framework for Statistical Timing Analysis using Non-Linear Delay and Slew Models

In this paper, we propose a framework for statistical static timing analysis (SSTA) considering intra-die process variations. Given a cell library, we propose an accurate method to characterize the gate and interconnect delay as well as slew as a function of underlying parameter variations. Using th...

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Bibliographic Details
Main Authors: Bhardwaj, S., Ghanta, P., Vrudhula, S.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Chaos
CMOS technology
Computer science
Delay lines
Integrated circuit interconnections
Libraries
Polynomials
Propagation delay
Random variables
Timing
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Description
Summary:In this paper, we propose a framework for statistical static timing analysis (SSTA) considering intra-die process variations. Given a cell library, we propose an accurate method to characterize the gate and interconnect delay as well as slew as a function of underlying parameter variations. Using these accurate delay models, we propose a method to perform SSTA based on a quadratic delay and slew model. The method is based on efficient dimensionality reduction technique used for accurate computation of the max of two delay expansions. Our results indicate less than 4% error in the variance of the delay models compared to SPICE Monte Carlo and less than 1% error in the variance of the circuit delay compared to Monte Carlo simulations
ISSN:1092-3152
1558-2434
DOI:10.1109/ICCAD.2006.320140