A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop Filter

• Main Authors: Tongyu Song, Zhiheng Cao, Shouli Yan
• Format: Conference Proceeding
• Language: English
• Subjects: Active noise reduction; Bandwidth; Clocks; CMOS technology; Feedback; Filters; Global Positioning System; Jitter; Prototypes; Signal design
• ISSN: 0886-5930; 2152-3630
• DOI: 10.1109/CICC.2006.320963

We present a 5 th -order continuous-time SigmaDelta modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time ΣΔ modulator with 2 MHz signal bandwidth is designed in a 0.25 μm CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype ΣΔ modulator achieves 68 dB dynamic range over 2 MHz bandwidth with a 150 MHz clock, consuming 1.8 mA from a 1.5 V supply.