A dual-band triple-mode SoC for 802.11a/b/g Embedded WLAN in 90nm CMOS

An 802.11a/b/g-compliant SoC integrates a WLAN system, comprising a dual-band RF transceiver and PHY, MAC and ARM processor units, in 90nm CMOS. Challenges of SoC integration in 90nm CMOS and the mitigation techniques are discussed, along with circuit design techniques to optimize RF performance in...

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Bibliographic Details
Main Authors: Shirvani, A., Cheung, D., Tsang, R., Jamal, S., Cho, T., Xiaodong Jin, Yonghua Song
Format: Conference Proceeding
Language:English
Subjects:
Circuit synthesis
CMOS process
Design optimization
Dual band
Physical layer
Power generation
Radio frequency
Transceivers
Transmitters
Wireless LAN
Online Access:Request full text
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Description
Summary:An 802.11a/b/g-compliant SoC integrates a WLAN system, comprising a dual-band RF transceiver and PHY, MAC and ARM processor units, in 90nm CMOS. Challenges of SoC integration in 90nm CMOS and the mitigation techniques are discussed, along with circuit design techniques to optimize RF performance in 90nm. For 54Mb/s signals, the receiver sensitivity is -75dBm/-72dBm at 2.4GHz/5GHz, where the transmitter achieves an EVM of -35dB/-32dB at 0dBm output power
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2006.320983