Signal Integrity Impact of Ultra Low Power IO Initiatives

I/O power represents a sizeable portion of the overall power budget on a low power mobile platform. Significant fraction of that I/O power is used to ensure signal integrity on the high speed buses. While there is flexibility to trade off I/O power consumption against signal quality on Intel's...

Full description

Saved in:
Bibliographic Details
Main Authors: Das, R., Yun Ji, S., Peterson, S., Chen, J.-U., Pan, C.
Format: Conference Proceeding
Language:English
Subjects:
Batteries
Electronics packaging
Energy consumption
Power dissipation
Power transmission lines
Routing
Termination of employment
Timing
Turning
Voltage
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:I/O power represents a sizeable portion of the overall power budget on a low power mobile platform. Significant fraction of that I/O power is used to ensure signal integrity on the high speed buses. While there is flexibility to trade off I/O power consumption against signal quality on Intel's current mobile and sub-note platforms, inefficiency still exists on wide I/O buses such as FSB and DDR2. In this paper, we will outline two novel bus termination schemes that can significantly reduce FSB and DDR2 I/O power consumption by further trading off signal quality on the new low power IA (LPIA) ultra small PC (UMPC) platforms
ISSN:2165-4107
DOI:10.1109/EPEP.2006.321177