Quadrature Direct Digital Frequency Synthesizer Using FPGA

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Such system is based on a classical DDFS structure. In order to avoid the high power consumption, no ROM is used but piecewise linear approximation is employed. The system is implemented using FPGA with 3.3 V supply vol...

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Bibliographic Details
Main Authors: Saber, M.S., Elmasry, M., Abo-Elsoud, M.E.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Communication switching
Energy consumption
Field programmable gate arrays
Frequency synthesizers
Low pass filters
Phase locked loops
Power engineering and energy
Read only memory
Wireless communication
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Summary:A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Such system is based on a classical DDFS structure. In order to avoid the high power consumption, no ROM is used but piecewise linear approximation is employed. The system is implemented using FPGA with 3.3 V supply voltage. The power consumption is 3.96 mW. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz
DOI:10.1109/ICCES.2006.320418