High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link

A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and en...

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Bibliographic Details
Main Authors: Dobkin, R., Perelman, Y., Liran, T., Ginosar, R., Kolodny, A.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Costs
Delay
Driver circuits
Integrated circuit interconnections
Power system interconnection
Shift registers
System-on-a-chip
Throughput
Transmitters
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Description
Summary:A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67 Gbps throughput in 65 nm technology. The serial link incurs lower power and area costs relative to bit-parallel communications, and enables higher tolerance to PVT variations relative to synchronous links. The link uses differential dual-rail level encoding (LEDR) and current mode signaling over a low-crosstalk interconnect layout. Novel circuits used in the link are described, including a novel splitter shift register, a fast LEDR encoder, a high-speed toggle element, a channel driver with adaptive control and a differential channel receiver.
ISSN:1522-8681
DOI:10.1109/ASYNC.2007.20