Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools lev...

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Bibliographic Details
Main Authors: Chelcea, T., Venkataramani, G., Goldstein, S.C.
Format: Conference Proceeding
Language:English
Subjects:
Asynchronous circuits
Circuit analysis
Circuit synthesis
Clocks
Computer science
Delay
Design automation
Design optimization
Logic
Timing
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Summary:Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous tool flows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal algorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding better average-case latencies than their synchronous counterparts.
ISSN:1522-8681
DOI:10.1109/ASYNC.2007.10