FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters

We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-processors. The architecture is highly scalable, has high temporal throughput (80 MHz or more temporal frame samples/second, per...

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Bibliographic Details
Main Authors: Arjuna Madanayake, H.L.P., Bruton, L.T.
Format: Conference Proceeding
Language:English
Subjects:
2D IIR
beam
broadband
Digital filters
Field programmable gate arrays
filter
FPGA
Frequency conversion
frequency-planar
IIR filters
Integrated circuit interconnections
Plane wave
Prototypes
Sensor arrays
Sensor phenomena and characterization
Throughput
Very large scale integration
Xilinx
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Description
Summary:We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-processors. The architecture is highly scalable, has high temporal throughput (80 MHz or more temporal frame samples/second, per sensor), and has excellent local interconnectivity. A single Xilinx Virtex-II xc2v2000 FPGA device circuit implementation is described for a highly selective first-order 2D infinite impulse response (IIR) broadband frequency-planar beam plane-wave filter, operating at a frame sample rate in excess of 80 MHz over a synchronously sampled linear sensor array consisting of 15 sensors and 15 A/D converters
DOI:10.1109/APCCAS.2006.342528