A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques

In this paper, a high-speed Baugh-Wooley multiplier using skew-tolerant domino techniques is presented. Compared with the conventional architecture, it is demonstrated that the performance is improved from the simulation results since the conventional multipliers suffer significant timing overhead d...

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Bibliographic Details
Main Authors: Steve Hung-Lung Tu, Chih-Hung Yen
Format: Conference Proceeding
Language:English
Subjects:
Adders
Central Processing Unit
Circuit simulation
clock skew
Clocks
CMOS logic circuits
Design engineering
domino circuit
Latches
Logic circuits
Merging
Multiplier
skew-tolerant domino
static circuit
Timing
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Summary:In this paper, a high-speed Baugh-Wooley multiplier using skew-tolerant domino techniques is presented. Compared with the conventional architecture, it is demonstrated that the performance is improved from the simulation results since the conventional multipliers suffer significant timing overhead due to system clock skew and logic path unbalance, which in turn decreases the performance of a circuit
DOI:10.1109/APCCAS.2006.342059