A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques

In this paper, a high-speed Baugh-Wooley multiplier using skew-tolerant domino techniques is presented. Compared with the conventional architecture, it is demonstrated that the performance is improved from the simulation results since the conventional multipliers suffer significant timing overhead d...

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Main Authors: Steve Hung-Lung Tu, Chih-Hung Yen
Format: Conference Proceeding
Language:English
Subjects:
Adders
Central Processing Unit
Circuit simulation
clock skew
Clocks
CMOS logic circuits
Design engineering
domino circuit
Latches
Logic circuits
Merging
Multiplier
skew-tolerant domino
static circuit
Timing
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Chih-Hung Yen
description In this paper, a high-speed Baugh-Wooley multiplier using skew-tolerant domino techniques is presented. Compared with the conventional architecture, it is demonstrated that the performance is improved from the simulation results since the conventional multipliers suffer significant timing overhead due to system clock skew and logic path unbalance, which in turn decreases the performance of a circuit
doi_str_mv 10.1109/APCCAS.2006.342059
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4145464</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4145464</ieee_id><sourcerecordid>4145464</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-64c066b076deecedb3cce1be06f7acc86441592f5d095725f6109b208ceb77e03</originalsourceid><addsrcrecordid>eNotj8tOg0AYhScxJprKC-hmXgD85w5LpGpNatRA47KB4YeOUkAuafr2kujZnG9x8iWHkFsGAWMQ3cfvSRKnAQfQgZAcVHRBvMiETHIpQYQ6vCLeOH7BEhEJI_U1-YjpxtUHP-0RS_qQzwt_dl2DZ_o6N5PrG4cDXePo6pbuRtfWNP3Gk58tkyFvJ7rujq7taIb20LqfGccbclnlzYjef6_I7ukxSzb-9u35JYm3vmNGTb6WFrQuwOgS0WJZCGuRFQi6Mrm1oZaSqYhXqoRIGa4qvVwsOIQWC2MQxIrc_XkdIu77wR3z4byXTCqppfgFSAxOfg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Steve Hung-Lung Tu ; Chih-Hung Yen</creator><creatorcontrib>Steve Hung-Lung Tu ; Chih-Hung Yen</creatorcontrib><description>In this paper, a high-speed Baugh-Wooley multiplier using skew-tolerant domino techniques is presented. Compared with the conventional architecture, it is demonstrated that the performance is improved from the simulation results since the conventional multipliers suffer significant timing overhead due to system clock skew and logic path unbalance, which in turn decreases the performance of a circuit</description><identifier>ISBN: 9781424403868</identifier><identifier>ISBN: 9781424403875</identifier><identifier>ISBN: 1424403871</identifier><identifier>ISBN: 1424403863</identifier><identifier>DOI: 10.1109/APCCAS.2006.342059</identifier><language>eng</language><publisher>IEEE</publisher><subject>Adders ; Central Processing Unit ; Circuit simulation ; clock skew ; Clocks ; CMOS logic circuits ; Design engineering ; domino circuit ; Latches ; Logic circuits ; Merging ; Multiplier ; skew-tolerant domino ; static circuit ; Timing</subject><ispartof>APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006, p.598-601</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4145464$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27916,54911</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4145464$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Steve Hung-Lung Tu</creatorcontrib><creatorcontrib>Chih-Hung Yen</creatorcontrib><title>A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques</title><title>APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems</title><addtitle>APCCAS</addtitle><description>In this paper, a high-speed Baugh-Wooley multiplier using skew-tolerant domino techniques is presented. Compared with the conventional architecture, it is demonstrated that the performance is improved from the simulation results since the conventional multipliers suffer significant timing overhead due to system clock skew and logic path unbalance, which in turn decreases the performance of a circuit</description><subject>Adders</subject><subject>Central Processing Unit</subject><subject>Circuit simulation</subject><subject>clock skew</subject><subject>Clocks</subject><subject>CMOS logic circuits</subject><subject>Design engineering</subject><subject>domino circuit</subject><subject>Latches</subject><subject>Logic circuits</subject><subject>Merging</subject><subject>Multiplier</subject><subject>skew-tolerant domino</subject><subject>static circuit</subject><subject>Timing</subject><isbn>9781424403868</isbn><isbn>9781424403875</isbn><isbn>1424403871</isbn><isbn>1424403863</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj8tOg0AYhScxJprKC-hmXgD85w5LpGpNatRA47KB4YeOUkAuafr2kujZnG9x8iWHkFsGAWMQ3cfvSRKnAQfQgZAcVHRBvMiETHIpQYQ6vCLeOH7BEhEJI_U1-YjpxtUHP-0RS_qQzwt_dl2DZ_o6N5PrG4cDXePo6pbuRtfWNP3Gk58tkyFvJ7rujq7taIb20LqfGccbclnlzYjef6_I7ukxSzb-9u35JYm3vmNGTb6WFrQuwOgS0WJZCGuRFQi6Mrm1oZaSqYhXqoRIGa4qvVwsOIQWC2MQxIrc_XkdIu77wR3z4byXTCqppfgFSAxOfg</recordid><startdate>200612</startdate><enddate>200612</enddate><creator>Steve Hung-Lung Tu</creator><creator>Chih-Hung Yen</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200612</creationdate><title>A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques</title><author>Steve Hung-Lung Tu ; Chih-Hung Yen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-64c066b076deecedb3cce1be06f7acc86441592f5d095725f6109b208ceb77e03</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Adders</topic><topic>Central Processing Unit</topic><topic>Circuit simulation</topic><topic>clock skew</topic><topic>Clocks</topic><topic>CMOS logic circuits</topic><topic>Design engineering</topic><topic>domino circuit</topic><topic>Latches</topic><topic>Logic circuits</topic><topic>Merging</topic><topic>Multiplier</topic><topic>skew-tolerant domino</topic><topic>static circuit</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Steve Hung-Lung Tu</creatorcontrib><creatorcontrib>Chih-Hung Yen</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Steve Hung-Lung Tu</au><au>Chih-Hung Yen</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques</atitle><btitle>APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems</btitle><stitle>APCCAS</stitle><date>2006-12</date><risdate>2006</risdate><spage>598</spage><epage>601</epage><pages>598-601</pages><isbn>9781424403868</isbn><isbn>9781424403875</isbn><isbn>1424403871</isbn><isbn>1424403863</isbn><abstract>In this paper, a high-speed Baugh-Wooley multiplier using skew-tolerant domino techniques is presented. Compared with the conventional architecture, it is demonstrated that the performance is improved from the simulation results since the conventional multipliers suffer significant timing overhead due to system clock skew and logic path unbalance, which in turn decreases the performance of a circuit</abstract><pub>IEEE</pub><doi>10.1109/APCCAS.2006.342059</doi><tpages>4</tpages></addata></record>
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Adders
Central Processing Unit
Circuit simulation
clock skew
Clocks
CMOS logic circuits
Design engineering
domino circuit
Latches
Logic circuits
Merging
Multiplier
skew-tolerant domino
static circuit
Timing
title A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T22%3A51%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20High-Speed%20Baugh-Wooley%20Multiplier%20Design%20Using%20Skew-Tolerant%20Domino%20Techniques&rft.btitle=APCCAS%202006%20-%202006%20IEEE%20Asia%20Pacific%20Conference%20on%20Circuits%20and%20Systems&rft.au=Steve%20Hung-Lung%20Tu&rft.date=2006-12&rft.spage=598&rft.epage=601&rft.pages=598-601&rft.isbn=9781424403868&rft.isbn_list=9781424403875&rft.isbn_list=1424403871&rft.isbn_list=1424403863&rft_id=info:doi/10.1109/APCCAS.2006.342059&rft_dat=%3Cieee_6IE%3E4145464%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-64c066b076deecedb3cce1be06f7acc86441592f5d095725f6109b208ceb77e03%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4145464&rfr_iscdi=true