A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm L gate , 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve f T /f MAX values of 360 GHz/420 GHz. PMOS transistors also demonstrate...

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Bibliographic Details
Main Authors: Post, I., Akbar, M., Curello, G., Gannavaram, S., Hafez, W., Jalan, U., Komeyii, K., Lin, J., Lindert, N., Park, J., Rizk, J., Sacks, G., Tsai, C., Yeh, D., Bai, P., Jan, C.-H.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Capacitance
CMOS technology
Cutoff frequency
MOS devices
MOSFETs
Q factor
Radio frequency
Scattering parameters
Silicon
Varactors
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Summary:Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm L gate , 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve f T /f MAX values of 360 GHz/420 GHz. PMOS transistors also demonstrate superior performance with f T /f MAX values of 238 GHz/295 GHz. Varactor performance on this substrate technology is also discussed
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2006.346816