Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized Interface

Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an "apparent" V T loss due to interface trap (N IT ) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this V T loss by blocking hydrogen from the interface. I...

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Main Authors: Shih, Y.H., Lai, E.K., Hsieh, J.Y., Hsu, T.H., Wu, M.D., Lu, C.P., Ni, K.P., Chou, T.Y., Yang, L.W., Hsieh, K.Y., Liaw, M.H., Lu, W.P., Chen, K.C., Ku, J., Ni, F.L., Liu, R., Chih-Yuan Lu
Format: Conference Proceeding
Language:English
Subjects:
Annealing
Degradation
Electrons
Failure analysis
Hydrogen
Nonvolatile memory
Oxidation
Silicon compounds
Temperature
Testing
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Summary:Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an "apparent" V T loss due to interface trap (N IT ) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this V T loss by blocking hydrogen from the interface. In this work we further outfit the ANS-ONO process with a nitridized Si/SiO 2 interface. By introducing a rapid thermal nitridation (RTN) after a low-energy buried diffusion (BD) implantation, the new process provides not only more immunity to HH-induced N IT generation but also a path to scale the BD. A 256Mb testing chip is successfully fabricated by the new approach with excellent natural good yield (>80%) and reliability. Our new process integration shows excellent reliability, scalability, and manufacturability for multi-bit/cell nitride trapping memory
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2006.346824