A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

• Main Authors: Nii, H., Sanuki, T., Okayama, Y., Ota, K., Iwamoto, T., Fujimaki, T., Kimura, T., Watanabe, R., Komoda, T., Eiho, A., Aikawa, K., Yamaguchi, H., Morimoto, R., Ohshima, K., Yokoyama, T., Matsumoto, T., Hachimine, K., Sogo, Y., Shino, S., Kanai, S., Yamazak, T., Takahashi, S., Maeda, H., Iwata, T., Ohno, K., Takegawa, Y., Oishi, A., Togo, M., Fukasaku, K., Takasu, Y., Yamasaki, H., Inokuma, H., Matsuo, K., Sato, T., Nakazawa, M., Katagiri, T., Nakazawa, K., Shinyama, T., Tetsuka, T., Fujita, S., Kagawa, Y., Nagaoka, K., Muramatsu, S., Iwasa, S., Mimotogi, S., Yoshida, K., Sunouchi, K., Iwai, M., Saito, M., Ikeda, M., Enomoto, Y., Naruse, H., Imai, K., Yamada, S., Nagashima, N., Kuwata, T., Matsuoka, F.
• Format: Conference Proceeding
• Language: English
• Subjects: Boron; CMOS technology; Degradation; DSL; Large scale integration; Lithography; Logic; MOSFET circuits; Random access memory; Surface-mount technology
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2006.346878

We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7)