Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub 50 nm Node DRAM

We report on the integration of sub-melt laser spike annealing (LSA) on W-gate stacked DRAM. We applied the LSA as a reactivation in back-end processes to comply with the considerable metal-pattern effects and strong DRAM thermal-budget. Improvements in drive currents of peripheral transistors (4 %/...

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Bibliographic Details
Main Authors: Gyoung Ho Buh, Guk-Hyon Yon, Tai-su Park, Jin-Wook Lee, Jihyun Kim, Yun Wang, Lucia Feng, Xiaoru Wang, Yu Gyun Shin, Siyoung Choi, U-In Chung, Joo-Tae Moon, Byung-Il Ryu
Format: Conference Proceeding
Language:English
Subjects:
Annealing
Contact resistance
Moon
Optical device fabrication
Power lasers
Radio control
Random access memory
Research and development
Semiconductor lasers
Thermal degradation
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Summary:We report on the integration of sub-melt laser spike annealing (LSA) on W-gate stacked DRAM. We applied the LSA as a reactivation in back-end processes to comply with the considerable metal-pattern effects and strong DRAM thermal-budget. Improvements in drive currents of peripheral transistors (4 %/14 % for n/p-FETs) are achieved by using the LSA without incurring short channel effect (SCE) while minimizing pattern effects of metal gate. DRAM cell transistors also show improvements in drive current, junction leakage, and GIDL (gate-induced drain leakage) without laser-induced local defects and reliability degradation
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2006.346918