Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors

Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS) source/drain transistors for the first time. DSS greatly improves propagation delay in multiple fan-in NAND gates at constant standby current. The delay is enhanced to 21% at 0.8V for 3-input NAND gates. Energy d...

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Bibliographic Details
Main Authors: Kinoshita, T., Hasumi, R., Hamaguchi, M., Miyashita, K., Komoda, T., Kinoshita, A., Koga, J., Adachi, K., Toyoshima, Y., Nakayama, T., Yamada, S., Matsuoka, F.
Format: Conference Proceeding
Language:English
Subjects:
CMOS logic circuits
CMOS technology
Decision support systems
FETs
Immune system
Large scale integration
Low voltage
MOSFETs
Propagation delay
Substrates
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Summary:Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS) source/drain transistors for the first time. DSS greatly improves propagation delay in multiple fan-in NAND gates at constant standby current. The delay is enhanced to 21% at 0.8V for 3-input NAND gates. Energy delay product (EDP) is improved by more than 50% with DSS at 0.8V
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2006.346961