Performance Evaluation of Two LMMSE Detectors in a MIMO-OFDM Hardware Testbed

The performance of two field programmable gate array (FPGA) implementations of a linear minimum mean square error (LMMSE) based detector is evaluated in realtime radio channels. Two square root free algorithms based on the QR decomposition (QRD) via Givens rotations, namely coordinate rotation digit...

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Main Authors: Myllyla, M., Juntti, M., Limingoja, M., Byman, A., Cavallaro, J.R.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Detectors
Field programmable gate arrays
Hardware
Mean square error methods
MIMO
OFDM
Sensor arrays
Systolic arrays
Testing
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creator Myllyla, M.
Juntti, M.
Limingoja, M.
Byman, A.
Cavallaro, J.R.
description The performance of two field programmable gate array (FPGA) implementations of a linear minimum mean square error (LMMSE) based detector is evaluated in realtime radio channels. Two square root free algorithms based on the QR decomposition (QRD) via Givens rotations, namely coordinate rotation digital computer (CORDIC) and squared Givens rotation (SGR) algorithms, are applied for the LMMSE detector implementation with pipelined systolic array architectures. The implementations are mapped to Elektrobit 2times2 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) hardware testbed for 4G MIMO systems (EB4G). The presented measurement results are done with a Propsim C8 MIMO channel emulator and compared to the simulated results.
doi_str_mv 10.1109/ACSSC.2006.354937
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Computer architecture
Detectors
Field programmable gate arrays
Hardware
Mean square error methods
MIMO
OFDM
Sensor arrays
Systolic arrays
Testing
title Performance Evaluation of Two LMMSE Detectors in a MIMO-OFDM Hardware Testbed
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