A Multi-Drop Transmission-Line Interconnect in Si LSI

This paper proposes a branching method for on-chip transmission line (TL) interconnects, which can reduce delay and power of global interconnects. A 6-mm-long TL interconnect with a branch is fabricated by using a 0.18 mum standard Si CMOS process, and the measurement result performs 4Gbps signal tr...

Full description

Saved in:
Bibliographic Details
Main Authors: Seita, J., Ito, H., Okada, K., Sato, T., Masu, K.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
CMOS process
Degradation
Delay
Impedance
Integrated circuit interconnections
Large scale integration
Peer to peer computing
Power transmission lines
Transmission lines
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper proposes a branching method for on-chip transmission line (TL) interconnects, which can reduce delay and power of global interconnects. A 6-mm-long TL interconnect with a branch is fabricated by using a 0.18 mum standard Si CMOS process, and the measurement result performs 4Gbps signal transmission.
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2007.357969