A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment

As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced b...

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Bibliographic Details
Main Authors: You-Gang Chen, I-Chyn Wey, An-Yeu Wu, A.
Format: Conference Proceeding
Language:English
Subjects:
Circuit noise
Circuit synthesis
Crosstalk
Dynamic voltage scaling
Mirrors
MOS devices
Noise reduction
Signal to noise ratio
Threshold voltage
Working environment noise
Online Access:Request full text
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Summary:As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.
DOI:10.1109/ASSCC.2006.357909