Pillar Bump Technology and Integrated Embedded Passive Devices

In this paper, we will discuss the copper pillar bump structure and comparison will be made with standard solder bump and its advantages. Temperature cycles and high temperature storage reliability on QFN using copper pillar bump were performed. Results show that copper pillar bump can withstand up...

Full description

Saved in:
Bibliographic Details
Main Authors: Asen Long Xin Jiang, Lai Chih Ming, Jeff Chen Yi Gao, Tan Kim Hwee
Format: Conference Proceeding
Language:English
Subjects:
Assembly
Bonding forces
Copper
Flip chip
Integrated circuit interconnections
Packaging
Space technology
Temperature
Tin
Wire
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, we will discuss the copper pillar bump structure and comparison will be made with standard solder bump and its advantages. Temperature cycles and high temperature storage reliability on QFN using copper pillar bump were performed. Results show that copper pillar bump can withstand up to 5000 cycles of mechanical stress test without mechanical and electrical failure. Electrical performance was discussed in term of current carrying density and comparison done with standard solder bump and its mean time to failure (MTTF) defined. The pillar bumps show that its MTTF is 2.3 times better than standard bump. JCAP (Jiangyin Changdian Advanced Packaging) uses the copper pillar bump technology and extend the technology to fabricate passive devices onto the chip. This application will improve the electrical performance and also the improve board space utilization
DOI:10.1109/ICEPT.2006.359812