A dynamically adaptive DSP for heterogeneous reconfigurable platforms

This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with res...

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Bibliographic Details
Main Authors: Campi, F., Deledda, A., Pizzotti, M., Ciccarelli, L., Rolandi, P., Mucci, C., Lodi, A., Vitkovski, A., Vanzolini, L.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Acceleration
Algorithm design and analysis
CMOS technology
Computer architecture
Digital signal processing
Digital signal processors
Embedded computing
Kernel
Signal design
Software tools
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Summary:This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with respect to state of the art are zero overhead for switching between successive configurations, relevant area and energy computational density on computational kernels (average of 2 GOPS/mm 2 , 0.2GOPS/mW) and relatively small area occupation (18 mm 2 ), making it suitable for acceleration or upgrade of multi-core heterogeneous embedded platforms. The processor is delivered with a software tool chain providing the application developer algorithmic analysis and design space exploration based on ANSI C, with no utilization of hardware-related constructs or description languages
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2007.364559