Implementation of AES/Rijndael on a dynamically reconfigurable architecture

Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. This paper presents the design of AES/Rijndael on a dynamically reconfigurable architecture. A performance improvement of three order of magnitude was s...

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Bibliographic Details
Main Authors: Mucci, C., Vanzolini, L., Lodi, A., Deledda, A., Guerrieri, R., Campi, F., Toma, M.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Cryptography
Data security
Field programmable gate arrays
Hardware
NIST
Reconfigurable architectures
Reduced instruction set computing
Software performance
Throughput
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Summary:Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. This paper presents the design of AES/Rijndael on a dynamically reconfigurable architecture. A performance improvement of three order of magnitude was shown compared to the reference code and up to 24times speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, a better energy efficiency with respect to the other programmable solutions was shown, obtaining up to 3 Mbit/sec/mW
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2007.364617