Fault Tolerant CMOS Logic Using Ternary Gates

In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary and multiple-valued logic (MVL). Signals are processed through capacitors in such a way that the logic operation of a gate...

Full description

Saved in:
Bibliographic Details
Main Authors: Berg, Y., Jensen, R., Lomsdalen, J., Gundersen, H., Aunet, S.
Format: Conference Proceeding
Language:English
Subjects:
Bridge circuits
Capacitors
Circuit faults
CMOS logic circuits
Fault tolerance
Joining processes
Logic gates
MOSFETs
Multivalued logic
Redundancy
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary and multiple-valued logic (MVL). Signals are processed through capacitors in such a way that the logic operation of a gate is independent of the DC voltage applied on the inputs. By combining signals through capacitors stuck on/stuck off and stuck at faults are not destructive when redundancy is applied. Simulated data for 130 nm and 0.35 mum CMOS processes are given.
ISSN:0195-623X
2378-2226
DOI:10.1109/ISMVL.2007.24