Failure Analysis of an Anomalous Subthreshold Current in Nano-Scale NAND Flash Memory

As the design rule of NAND-type memory decreases down to sub 100 nm tech regime, one of important problems is the control of the parasitic transistor phenomenon. The parasitic transistor which causes subthreshold kink at high substrate bias is a common phenomenon for STI (shallow trench isolation) t...

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Main Authors: Dong-Ho Lee, Seung-Woo Shin, Choon-Kun Ryu, Jae-Hoon Choi, Chae-Moon Lim, Noh-Yeal Kwak, Hyun-Soo Shon, Jaehyoung Koo, Kwon Hong, Byung-Seok Lee, Sung-Ki Park, Sung-Wook Park, Kae-Dal Kwack
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Degradation
Fabrication
Failure analysis
Implants
Isolation technology
Nanoscale devices
Numerical simulation
Silicon devices
Subthreshold current
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Summary:As the design rule of NAND-type memory decreases down to sub 100 nm tech regime, one of important problems is the control of the parasitic transistor phenomenon. The parasitic transistor which causes subthreshold kink at high substrate bias is a common phenomenon for STI (shallow trench isolation) technology, especially for isolation whose pitch needs to be shrunk. To resolve the degradation of device performance by the subthreshold hump, many process solution has been reported (Park, 2000). Furthermore, in the fabrication of nano-scale silicon device, accurate 2D failure analysis is one of the important fields to be solved. In this paper, we present the numerical simulation study of STI implant process factor to suppress anomalous hump effect and investigate feasibility of the application of scanning capacitance microscopy (SCM) and chemical staining method in 2D failure analysis of 70nm NAND flash device
ISSN:1541-7026
1938-1891
DOI:10.1109/RELPHY.2007.369976