FPGA Prototyping Strategy for a H.264/AVC Video Decoder

This paper presents the prototyping strategy used to validate the designed modules of a main profile H.264/AVC video decoder designed to achieve 1080p HDTV resolution, implemented in a FPGA. All modules designed were completely described in VHDL and further validated through simulations. The post pl...

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Bibliographic Details
Main Authors: Rosa, V.S., Staehler, W.T., Azevedo, A., Zatt, B., Porto, R.E., Agostini, L.V., Bampi, S., Susin, A.A.
Format: Conference Proceeding
Language:English
Subjects:
Automatic voltage control
Decoding
Digital TV
Field programmable gate arrays
Filters
Hardware
Informatics
Prototypes
Software prototyping
Video compression
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Summary:This paper presents the prototyping strategy used to validate the designed modules of a main profile H.264/AVC video decoder designed to achieve 1080p HDTV resolution, implemented in a FPGA. All modules designed were completely described in VHDL and further validated through simulations. The post place-and-route synthesis results indicate that the designed architectures are able to target real time when processing HDTV 1080p frames (1080times1920). The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The prototyping strategy used an embedded Power PC and associated logic and buffering to control the modules under prototyping. A host computer, running the reference software, was used to generate the input stimuli and to compare the results, through a RS-232 serial interface.
ISSN:2150-5500
2150-5519
DOI:10.1109/RSP.2007.23