Multi-layer Copper-Dielectric Adhesion Challenges of 5-12 micron Lines/Spaces for Next Generation SOP (System-on-Package) / Microprocessor Package Substrates

• Main Authors: Wiedenman, B., Sundaram, V., Fuhan Liu, Krishnan, G., Roberts, H., Brooks, P., Johal, K., Iyer, M., Tummala, R.R.
• Format: Conference Proceeding
• Language: English
• Subjects: Adhesives; Copper; Dielectric substrates; Dielectric thin films; Microprocessors; Moore's Law; Packaging; Space technology; Surface treatment; Wiring
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2007.373983

System-On-Package (SOP) is a highly integrated systems packaging technology for convergent computing, communication, consumer, and bio-electronic functions in a single package or module. SOP aims to miniaturize systems by the integration of system-level components at microscale in the short term and nanoscale in the future. A key challenge for active and passive component integration is the demand for additional fine pitch wiring in the substrate for interconnecting these thin film embedded components. This adds to the already escalating need for high wiring density substrates driven by transistor density on the IC (Moore's Law). This paper addresses a critical process technology for SOP/microprocessor ultra-high density organic build-up substrates, namely, surface treatment of copper and dielectric in multilayer wiring. This process is critical for the challenges of processing and maintaining signal integrity at lines and spaces below 12μm. A complete description of fine line and space fabrication and a novel copper adhesion process and its operating parameters are presented. We demonstrate this process with superior bonding strength through accelerated reliability testing. Results are shown not only state-of-the-art build-up films but also for high-performance substrates and prepregs in comparison to more traditional copper roughening treatment methods.