Digital Inverse Timing Generator with Wide Dynamic Range

This paper addresses a timing generator with an output inversely proportional to a binary input without involving cost/area intensive digital division hardware or DSP processor based solution. The timing generation is based on interpreting a binary input as a floating point number (step value) and s...

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Main Authors: Kannan, Bharath Balaji, Ngo, Khai D.T.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Costs
Dynamic range
Hardware
Proportional control
Pulse generation
Pulse width modulation
Pulse width modulation converters
Timing
Voltage control
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Ngo, Khai D.T.
description This paper addresses a timing generator with an output inversely proportional to a binary input without involving cost/area intensive digital division hardware or DSP processor based solution. The timing generation is based on interpreting a binary input as a floating point number (step value) and successively accumulating it to a predefined count. A unique scaling process generates the step value required for accumulation from the binary input and also alleviates the requirement for a high clock frequency. The functionality of the proposed architecture was experimentally verified with implementation on an ALTERA CPLD EPF10K70 clocked at 25.175MHz. The dynamic range extends from 355ns to 17μs.
doi_str_mv 10.1109/ISCAS.2007.378398
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Clocks
Costs
Dynamic range
Hardware
Proportional control
Pulse generation
Pulse width modulation
Pulse width modulation converters
Timing
Voltage control
title Digital Inverse Timing Generator with Wide Dynamic Range
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