A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop

A fully-differential 2-GHz phase-locked loop (PLL) was designed and fabricated in 0.18-μm CMOS process. The PLL rejects the common noise due to fully-differential VCO and differential charge pump. The VCO has a 16.15% tuning range (from 1.8998GHz to 2.2335GHz) due to a combination of analog and digi...

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Main Authors: Li Zhang, Chi, Baoyong, Wang, Zhihua, Chen, Hongyi, Yao, Jinke, Wu, Ende
Format: Conference Proceeding
Language:English
Subjects:
Charge pumps
CMOS process
Filters
Phase frequency detector
Phase locked loops
Phase noise
Transceivers
Transfer functions
Tuning
Voltage-controlled oscillators
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creator Li Zhang
Chi, Baoyong
Wang, Zhihua
Chen, Hongyi
Yao, Jinke
Wu, Ende
description A fully-differential 2-GHz phase-locked loop (PLL) was designed and fabricated in 0.18-μm CMOS process. The PLL rejects the common noise due to fully-differential VCO and differential charge pump. The VCO has a 16.15% tuning range (from 1.8998GHz to 2.2335GHz) due to a combination of analog and digital tuning technique (4-bit binary switch-capacitor array). With the pn-junction varactors, the phase noise of the VCO varies only about 2dB in the tuning range. The current consumption of the PLL is only about 6.1mA from a 1.8V power supply. It is comparable to the results reported in recent literatures. The phase noise of the PLL at 2.033GHz can achieve -117.17dBc/Hz at 1 MHz frequency offset from the carrier.
doi_str_mv 10.1109/ISCAS.2007.378615
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source IEEE Xplore All Conference Series
subjects Charge pumps
CMOS process
Filters
Phase frequency detector
Phase locked loops
Phase noise
Transceivers
Transfer functions
Tuning
Voltage-controlled oscillators
title A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop
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