Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology

This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240MHz frequency range have been realized in 0.18 μ m standard CMOS process, with a 1.8V power supply voltage. A comparison between realigned and not re...

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Bibliographic Details
Main Authors: Roubadia, Regis, Ajram, Sami, Cathebras, Guy
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Clocks
CMOS technology
Energy consumption
Frequency
Jitter
Phase locked loops
Phase noise
Power supplies
Voltage-controlled oscillators
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Summary:This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240MHz frequency range have been realized in 0.18 μ m standard CMOS process, with a 1.8V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240MHz without increasing the power consumption, which is 2.4mW at 240MHz.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2007.378744