Global critical path: a tool for system-level timing analysis

An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is defined at the RTL level, as the longest path in the combinational logic between clocked registers. In this paper, we pr...

Full description

Saved in:
Bibliographic Details
Main Authors: Venkataramani, Girish, Budiu, Mihai, Chelcea, Tiberiu, Goldstein, Seth C.
Format: Conference Proceeding
Language:English
Subjects:
Automatic control
Circuits
Clocks
Control systems
Design
Design optimization
Global critical path
Hardware
Hardware > Hardware validation
Hardware profiling
Logic
Measurement
Performance analysis
Registers
System modeling
Timing
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is defined at the RTL level, as the longest path in the combinational logic between clocked registers. In this paper, we present a system-level timing analysis technique to define the concept of a Global Critical Path (GCP), for predicting system-level performance. We show how the GCP can be used as a theoretical and practical tool for understanding, summarizing and optimizing the behavior of highly concurrent self-timed circuits. We formally define the GCP and show how it can be constructed using a discrete event model and hardware profiling techniques. The GCP provides valuable insight into the control-path behavior of circuits and in finding system-level bottlenecks. We have incorporated the GCP construction and analysis framework into a high-level synthesis and simulation toolchain, thus enabling complete automation in modeling, analysis and optimization.
ISSN:0738-100X
DOI:10.1145/1278480.1278675