A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD. Fine locking is achieved by the phase...

Full description

Saved in:
Bibliographic Details
Main Authors: Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS process
CMOS technology
Delay effects
Feedback circuits
Mirrors
Phase detection
Phase locked loops
Phase shifters
Pulse inverters
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD. Fine locking is achieved by the phase shifter for the sake of fast locking. Measure results show that the maximum clock skew of the proposed SMD is 33.64ps in the frequency range from 200 to 450MHz and that the consumption power is 9.71mW at 450MHz in a 0.18-μm 1P6M N-well CMOS process at 1.8V power supply. The total locking time is less than 10 clock cycles.
DOI:10.1109/ICECS.2006.379852