A LVDS Serial AER Link

Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that tran...

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Bibliographic Details
Main Authors: Miro-Amarante, L., Jimenez, A., Linares-Barranco, A., Gomez-Rodriguez, F., Paz, R., Jimenez, G., Civit, A., Serrano-Gotarredona, R.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Communication cables
Convolutional codes
Frequency
Magnetic noise
Noise cancellation
Pins
Protocols
Real time systems
Retina
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Summary:Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows to analyse a LVDS Serial AER link. The interface allows up to 0.7 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.
DOI:10.1109/ICECS.2006.379944