A Delay Characterization Method for Integrated Devices

We present in this paper a new approach for on-chip delay characterization of integrated passive and active devices such as transistors, interconnects and analog resistors and capacitors. The proposed method is a time-domain technique that uses on-chip configurable ring oscillators to characterize i...

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Bibliographic Details
Main Authors: Lafrance, L-P., Savaria, Y.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance measurement
Circuit testing
Driver circuits
Electrical resistance measurement
Integrated circuit interconnections
Integrated circuit measurements
Inverters
Parasitic capacitance
Propagation delay
Resistors
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Description
Summary:We present in this paper a new approach for on-chip delay characterization of integrated passive and active devices such as transistors, interconnects and analog resistors and capacitors. The proposed method is a time-domain technique that uses on-chip configurable ring oscillators to characterize independently dynamic parasitic resistance and capacitance of the device under characterization. With the use of empirical techniques, based on interpolated look-up tables of pre-simulated data, the method achieves very good estimates of capacitance and resistance. A calibration technique to compensate process variations is also proposed and validated. The proposed method is implemented on a chip, designed in the CMOS 180nm TSMC technology. The chip was manufactured and is currently under verification.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2006.382118