A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

A novel topology of phase detector (PD) for applications in clock recovery systems from nonreturn-to-zero data is presented in this paper. The PD operates directly on the data stream, without requiring preprocessing, and behaves like a sampling-type PD, providing a sinusoidal phase characteristic. T...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2007-08, Vol.54 (8), p.1626-1635
Main Authors: Centurelli, F., Scotti, G., Trifiletti, A.
Format: Article
Language:English
Subjects:
Circuit topology
Circuits
Clock recovery
Clocks
CMOS technology
Design engineering
Detectors
Germanium silicon alloys
High speed
optical communication
Optical fiber communication
Optical signal processing
Phase detection
phase detector (PD)
Phase detectors
Phase locked loops
phase-locked loop (PLL)
Preprocessing
Silicon germanium
Specifications
Topology
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A novel topology of phase detector (PD) for applications in clock recovery systems from nonreturn-to-zero data is presented in this paper. The PD operates directly on the data stream, without requiring preprocessing, and behaves like a sampling-type PD, providing a sinusoidal phase characteristic. The triple-tail cell principle is exploited to obtain a circuit topology suitable to low-voltage high-speed applications, with a very simple structure and thus limited jitter generation. A model is proposed to understand circuit behavior and optimize its design. The PD has been used in a clock-and-data recovery circuit for 10-Gb/s optical communications, and measurements in agreement with SONET specifications are reported.
ISSN:1549-8328
1057-7122
1558-0806
DOI:10.1109/TCSI.2007.902414