Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems

Scalability of architecture, programming model and task control management will be a major challenge for MP-SOC designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-S...

Full description

Saved in:
Bibliographic Details
Main Authors: Saint-Jean, N., Benoit, P., Sassatelli, G., Torres, L., Robert, M.
Format: Conference Proceeding
Language:English
Subjects:
Application software
CMOS technology
Computer architecture
Hardware
Network-on-a-chip
Operating systems
Reduced instruction set computing
Runtime
Scalability
Semiconductor device modeling
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Scalability of architecture, programming model and task control management will be a major challenge for MP-SOC designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-SOC. The hardware architecture, H-Scale, is a homogeneous MP-SOC based on RISC processors, distributed memories and a globally asynchronous/locally synchronous network on chip. S-Scale is the software support to program H-Scale. It is a multithreaded sequential programming model with dedicated communication primitives handled at run-time by a simple operating system we developed. The hardware validations on FPGA and CMOS 90 nm technology and the experimental case studies on several applications (FIR, DES and MJPEG) demonstrate the scalability of our approach and draws interesting perspectives to automate task placement and duplication.
DOI:10.1109/ICSAMOS.2007.4285738