An 8-b 1-GSmaples/s CMOS Cascaded Folding and Interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The cir...

Full description

Saved in:
Bibliographic Details
Main Authors: Zhu, Xubin, Ni, Weining, Zhang, Qiang, Shi, Yin
Format: Conference Proceeding
Language:English
Subjects:
Analog-digital conversion
Analog-to-Digital converter
cascading
Circuit topology
CMOS analog integrated circuit
CMOS analog integrated circuits
CMOS technology
Differential amplifiers
folding-and-interpolating
Low voltage
Sampling methods
Switched capacitor circuits
Switches
Switching circuits
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-μm CMOS technology, and measures 1.47 mm × 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.
DOI:10.1109/EDST.2007.4289804