A Delay Circuit for Build-Out-Self-Test in 0.18-μm CMOS

This paper describes a digital controlled delay circuit for BOST(build-out-self-test) with picosecond resolution. The proposed circuit operates at 250MHz under 1.8V supply according to Hspice simulation on the extracted layout. The complete design was fabricated in a standard TSMC 0.18μm CMOS proces...

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Bibliographic Details
Main Authors: Li Tianmao, Toshifumi, Hasimoto, Yukinori, Kuroki
Format: Conference Proceeding
Language:English
Subjects:
Circuit testing
CMOS integrated circuit
Coarse
Delay effects
Delay lines
Digital control
Fine
Inverters
low-voltage design
MOS capacitors
Multiplexing
Phase locked loop
Phase locked loops
Switches
Voltage-controlled oscillators
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Description
Summary:This paper describes a digital controlled delay circuit for BOST(build-out-self-test) with picosecond resolution. The proposed circuit operates at 250MHz under 1.8V supply according to Hspice simulation on the extracted layout. The complete design was fabricated in a standard TSMC 0.18μm CMOS process technology. The proposed circuit draws 7mw of static power and occupies an area of 0.09mm 2 .
DOI:10.1109/EDST.2007.4289811