A Radiation Hardened by Design Register File With Lightweight Error Detection and Correction

A radiation hardened by design 32times36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and fi...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 2007-08, Vol.54 (4), p.1335-1342
Main Authors: Mohr, K.C., Samson, G., Clark, L.T.
Format: Article
Language:English
Subjects:
Accelerated tests
Cache memory
CMOS
CMOS process
Delay
Error correction
Error detection
Error detection and correction (EDAC)
Field programmable gate arrays
Foundries
Life estimation
Lightweight
Radiation detectors
Radiation hardening
register file
Registers
Soft errors
Testing
Weight reduction
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A radiation hardened by design 32times36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 mum bulk CMOS process with a measured speed over 1 GHz at V DD =1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2007.903173