Scaling Limits of Double-Gate and Surround-Gate Z-RAM Cells

We consider the scaling of the capacitorless single-transistor [zero-capacitor RAM (Z-RAM)] dynamic RAM (DRAM) cells having surround-gate and double-gate structures. We find that the scaling is limited to the channel length of approximately 25 nm for both types of cells, which is somewhat more pessi...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2007-09, Vol.54 (9), p.2255-2262
Main Authors: Butt, N.Z., Alam, M.A.
Format: Article
Language:English
Subjects:
Capacitorless
Capacitors
Carriers
Channels
Devices
double gate
Dynamic random access memory
Dynamics
Fluctuation
Impact ionization
Logic gates
Mathematical model
Noise
Quantum confinement
Random access memory
scaling
simulation
surround gate
Transistors
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Summary:We consider the scaling of the capacitorless single-transistor [zero-capacitor RAM (Z-RAM)] dynamic RAM (DRAM) cells having surround-gate and double-gate structures. We find that the scaling is limited to the channel length of approximately 25 nm for both types of cells, which is somewhat more pessimistic than previously believed. The mechanisms that are found to be of most importance in imposing the scaling limits are as follows: 1) short-channel effects; 2) quantum confinement of carriers in the body; and 3) band-to-band tunneling at the source/drain-to-body junctions. Like other DRAM cells, practical considerations such as the process variations in cell dimensions, random doping fluctuations, and single-event upsets are likely to remain as important scaling concerns for Z-RAM cells.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2007.902691