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Trench-Isolated High-Voltage IC with Reduced Parasitic Bipolar Transistor Action
For high-voltage IC device, one of the important issues is to prevent parasitic transistor acting, especially in junction-isolation (JI) device. In addition to this problem, it is necessary to achieve it by a minimum cost. In this paper, we propose junction-isolated HVIC using deep trench-isolation...
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Main Authors: | , , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
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Summary: | For high-voltage IC device, one of the important issues is to prevent parasitic transistor acting, especially in junction-isolation (JI) device. In addition to this problem, it is necessary to achieve it by a minimum cost. In this paper, we propose junction-isolated HVIC using deep trench-isolation techniques. And we examined about structures of reducing parasitic transistor action by simulation and experiments. In proposed structures, the area of isolation is reduced to 2/3 to 1/2 compared with conventional junction isolation. Moreover, significant reduction of hFE of parasitic transistor in logic transistors and HV-transistor are confirmed. |
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ISSN: | 1063-6854 1946-0201 |
DOI: | 10.1109/ISPSD.2007.4294934 |