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Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis
In hard real-time applications, WCET is used to check time constraints of the whole system but is only computed at the task level. While most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect h...
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| creator | Nemer, F. Casse, H. Sainrat, P. Awada, A. |
| description | In hard real-time applications, WCET is used to check time constraints of the whole system but is only computed at the task level. While most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware facilities should improve the accuracy of the result. As an example, we developed an analysis of a direct-mapped instruction cache behavior, that combines inter-and intra-task instruction cache analysis to estimate more accurately the number of cache misses due to task chaining by considering task entry and exit states along the inter-task analysis. The initial tasks WCET can be computed by any existing single-task approach that models the instruction cache behavior. |
| doi_str_mv | 10.1109/SIES.2007.4297313 |
| format | conference_proceeding |
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| identifier | ISSN: 2150-3109 |
| ispartof | 2007 International Symposium on Industrial Embedded Systems, 2007, p.25-32 |
| issn | 2150-3109 2150-3117 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application software Cause effect analysis Computer aided instruction Computer science Data analysis Data Flow Analyses Hardware Performance analysis Processor scheduling Real time systems Timing Worst Case Execution Time |
| title | Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis |
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