Process State Machines for Behavioral Modeling of Embedded Systems

In the embedded systems and SoC (system-on-chip) area, we defined a model-driven HW-SW co-design methodology based on the UML 2, a SystemC UML profile for the HW side, and a multi-threaded C UML profile for the SW side, which allows modeling of the system at higher levels of abstraction (from a func...

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Bibliographic Details
Main Authors: Bocchio, S., Riccobene, E., Rosti, A., Scandurra, P.
Format: Conference Proceeding
Language:English
Subjects:
Design engineering
Embedded system
Embedded Systems and SoC design
Model driven engineering
Performance analysis
Productivity
Proposals
Real time systems
System-on-a-chip
SystemC
Timing
UML statemachines
Unified modeling language
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Description
Summary:In the embedded systems and SoC (system-on-chip) area, we defined a model-driven HW-SW co-design methodology based on the UML 2, a SystemC UML profile for the HW side, and a multi-threaded C UML profile for the SW side, which allows modeling of the system at higher levels of abstraction (from a functional executable level to register transfer level) - far beyond the capabilities of existing HDLs. In this paper, we present the SystemC Process State Machines, an extension of the UML state machine formalism, that we defined as part of the SystemC UML profile to model the reactive behavior and concurrency aspects of SoC components, abstracting the SystemC design primitives available for this scope and guaranteeing straightforward translation to SystemC code.
ISSN:2150-3109
2150-3117
DOI:10.1109/SIES.2007.4297345