3-D Topologies for Networks-on-Chip

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2007-10, Vol.15 (10), p.1081-1090
• Main Authors: Pavlidis, V.F., Friedman, E.G.
• Format: Article
• Language: English
• Subjects: 3-D circuits; 3-D integrated circuits (ICs); 3-D integration; Channels; Circuit topology; CMOS technology; Communication channels; Consumer electronics; Delay; Energy consumption; Integrated circuit interconnections; Network topology; Network-on-a-chip; Networks; networks-on-chip (NoC); Performance analysis; Planes; Power consumption; Studies; Three dimensional; topologies; Topology; Two dimensional; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2007.893649

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3D structures. An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40% and 36% and a decrease of 62% and 58% in power consumption is demonstrated for 3D NoC as compared to a traditional 2D NoC topology for a network size of N = 128 and N = 256 nodes, respectively.