A New Class of Single Event Soft Errors

A new class of single event transient errors, referred to here as "single event disturb errors", is described. These errors are potentially as troublesome as single event upsets. Computer simulations demonstrate that disturb errors have critical charges less than or equal to those for logi...

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Published in:IEEE transactions on nuclear science 1984-01, Vol.31 (6), p.1145-1148
Main Author: Diehl-Nagle, Sherra E.
Format: Article
Language:English
Subjects:
Circuit testing
Computer errors
Computer simulation
Drives
Error correction
Integrated circuit interconnections
Logic
Read-write memory
Resistors
Single event upset
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cited_by cdi_FETCH-LOGICAL-c261t-c34f96b48681afcf0b7271b2bc771667e417a329b4bbe986c8e665906d8548a93
cites cdi_FETCH-LOGICAL-c261t-c34f96b48681afcf0b7271b2bc771667e417a329b4bbe986c8e665906d8548a93
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container_issue 6
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container_title IEEE transactions on nuclear science
container_volume 31
creator Diehl-Nagle, Sherra E.
description A new class of single event transient errors, referred to here as "single event disturb errors", is described. These errors are potentially as troublesome as single event upsets. Computer simulations demonstrate that disturb errors have critical charges less than or equal to those for logic upset in all circuits, and rates approaching those for upset in state-of-the-art sRAM circuits with polysilicon resistor loads. The errors cannot be prevented by resistive decoupling, and elude many current single event error testing methods.
doi_str_mv 10.1109/TNS.1984.4333472
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fullrecord <record><control><sourceid>crossref_ieee_</sourceid><recordid>TN_cdi_ieee_primary_4333472</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4333472</ieee_id><sourcerecordid>10_1109_TNS_1984_4333472</sourcerecordid><originalsourceid>FETCH-LOGICAL-c261t-c34f96b48681afcf0b7271b2bc771667e417a329b4bbe986c8e665906d8548a93</originalsourceid><addsrcrecordid>eNo9j81LwzAYxoMoWDfvgpfcPLXmbb6Po9QPGNuh8xySmEilrpIUxf_ejk1PDw_PB_wQugFSARB9v9t0FWjFKkYpZbI-QwVwrkrgUp2jghBQpWZaX6KrnN9nyzjhBbpb4U34xs1gc8ZjxF2_fxsCbr_CfsLdGCfcpjSmvEQX0Q45XJ90gV4e2l3zVK63j8_Nal36WsBUesqiFo4pocBGH4mTtQRXOy8lCCEDA2lprR1zLmglvApCcE3Eq-JMWU0XiBx_fRpzTiGaz9R_2PRjgJgDqJlBzQHUnEDnye1x0ocQ_ut_6S_ak0x3</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>A New Class of Single Event Soft Errors</title><source>IEEE Xplore (Online service)</source><creator>Diehl-Nagle, Sherra E.</creator><creatorcontrib>Diehl-Nagle, Sherra E.</creatorcontrib><description>A new class of single event transient errors, referred to here as "single event disturb errors", is described. These errors are potentially as troublesome as single event upsets. Computer simulations demonstrate that disturb errors have critical charges less than or equal to those for logic upset in all circuits, and rates approaching those for upset in state-of-the-art sRAM circuits with polysilicon resistor loads. The errors cannot be prevented by resistive decoupling, and elude many current single event error testing methods.</description><identifier>ISSN: 0018-9499</identifier><identifier>EISSN: 1558-1578</identifier><identifier>DOI: 10.1109/TNS.1984.4333472</identifier><identifier>CODEN: IETNAE</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit testing ; Computer errors ; Computer simulation ; Drives ; Error correction ; Integrated circuit interconnections ; Logic ; Read-write memory ; Resistors ; Single event upset</subject><ispartof>IEEE transactions on nuclear science, 1984-01, Vol.31 (6), p.1145-1148</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c261t-c34f96b48681afcf0b7271b2bc771667e417a329b4bbe986c8e665906d8548a93</citedby><cites>FETCH-LOGICAL-c261t-c34f96b48681afcf0b7271b2bc771667e417a329b4bbe986c8e665906d8548a93</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4333472$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Diehl-Nagle, Sherra E.</creatorcontrib><title>A New Class of Single Event Soft Errors</title><title>IEEE transactions on nuclear science</title><addtitle>TNS</addtitle><description>A new class of single event transient errors, referred to here as "single event disturb errors", is described. These errors are potentially as troublesome as single event upsets. Computer simulations demonstrate that disturb errors have critical charges less than or equal to those for logic upset in all circuits, and rates approaching those for upset in state-of-the-art sRAM circuits with polysilicon resistor loads. The errors cannot be prevented by resistive decoupling, and elude many current single event error testing methods.</description><subject>Circuit testing</subject><subject>Computer errors</subject><subject>Computer simulation</subject><subject>Drives</subject><subject>Error correction</subject><subject>Integrated circuit interconnections</subject><subject>Logic</subject><subject>Read-write memory</subject><subject>Resistors</subject><subject>Single event upset</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1984</creationdate><recordtype>article</recordtype><recordid>eNo9j81LwzAYxoMoWDfvgpfcPLXmbb6Po9QPGNuh8xySmEilrpIUxf_ejk1PDw_PB_wQugFSARB9v9t0FWjFKkYpZbI-QwVwrkrgUp2jghBQpWZaX6KrnN9nyzjhBbpb4U34xs1gc8ZjxF2_fxsCbr_CfsLdGCfcpjSmvEQX0Q45XJ90gV4e2l3zVK63j8_Nal36WsBUesqiFo4pocBGH4mTtQRXOy8lCCEDA2lprR1zLmglvApCcE3Eq-JMWU0XiBx_fRpzTiGaz9R_2PRjgJgDqJlBzQHUnEDnye1x0ocQ_ut_6S_ak0x3</recordid><startdate>19840101</startdate><enddate>19840101</enddate><creator>Diehl-Nagle, Sherra E.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>19840101</creationdate><title>A New Class of Single Event Soft Errors</title><author>Diehl-Nagle, Sherra E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c261t-c34f96b48681afcf0b7271b2bc771667e417a329b4bbe986c8e665906d8548a93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1984</creationdate><topic>Circuit testing</topic><topic>Computer errors</topic><topic>Computer simulation</topic><topic>Drives</topic><topic>Error correction</topic><topic>Integrated circuit interconnections</topic><topic>Logic</topic><topic>Read-write memory</topic><topic>Resistors</topic><topic>Single event upset</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Diehl-Nagle, Sherra E.</creatorcontrib><collection>CrossRef</collection><jtitle>IEEE transactions on nuclear science</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Diehl-Nagle, Sherra E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A New Class of Single Event Soft Errors</atitle><jtitle>IEEE transactions on nuclear science</jtitle><stitle>TNS</stitle><date>1984-01-01</date><risdate>1984</risdate><volume>31</volume><issue>6</issue><spage>1145</spage><epage>1148</epage><pages>1145-1148</pages><issn>0018-9499</issn><eissn>1558-1578</eissn><coden>IETNAE</coden><abstract>A new class of single event transient errors, referred to here as "single event disturb errors", is described. These errors are potentially as troublesome as single event upsets. Computer simulations demonstrate that disturb errors have critical charges less than or equal to those for logic upset in all circuits, and rates approaching those for upset in state-of-the-art sRAM circuits with polysilicon resistor loads. The errors cannot be prevented by resistive decoupling, and elude many current single event error testing methods.</abstract><pub>IEEE</pub><doi>10.1109/TNS.1984.4333472</doi><tpages>4</tpages></addata></record>
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1558-1578
language eng
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source IEEE Xplore (Online service)
subjects Circuit testing
Computer errors
Computer simulation
Drives
Error correction
Integrated circuit interconnections
Logic
Read-write memory
Resistors
Single event upset
title A New Class of Single Event Soft Errors
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T09%3A20%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20New%20Class%20of%20Single%20Event%20Soft%20Errors&rft.jtitle=IEEE%20transactions%20on%20nuclear%20science&rft.au=Diehl-Nagle,%20Sherra%20E.&rft.date=1984-01-01&rft.volume=31&rft.issue=6&rft.spage=1145&rft.epage=1148&rft.pages=1145-1148&rft.issn=0018-9499&rft.eissn=1558-1578&rft.coden=IETNAE&rft_id=info:doi/10.1109/TNS.1984.4333472&rft_dat=%3Ccrossref_ieee_%3E10_1109_TNS_1984_4333472%3C/crossref_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c261t-c34f96b48681afcf0b7271b2bc771667e417a329b4bbe986c8e665906d8548a93%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4333472&rfr_iscdi=true