Empirical Modeling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips

A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a thre...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 1986-12, Vol.33 (6), p.1581-1585
Main Authors: Zoutendyk, J. A., Smith, L. S., Soli, G. A., Smith, S. L., Atwood, G. E., Thieberger, P.
Format: Article
Language:English
Subjects:
Electronics And Electrical Engineering
Integrated circuit modeling
Integrated circuit technology
Ion accelerators
Laboratories
MOS devices
Process design
Random access memory
Read-write memory
Single event upset
Variable structure systems
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Summary:A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.1986.4334645