Advanced Poly-Si NMIS and Poly-Si/TiN PMIS Hybrid-Gate High-k CMIS using PVD/CVD-Stacked TiN and Local Strain Technique

Performance of advanced hybrid-gate CMOS (poly-Si/HfSiON nMIS and poly-Si/TiN/HfSiON pMIS) is demonstrated. V th of pMIS is controlled by fluorine implantation and by PVD/CVD-stacked TiN, which has higher WF than conventional single-CVD TiN. This combination enables sufficient V th -control without...

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Bibliographic Details
Main Authors: Nishida, Y., Kawahara, T., Sakashita, S., Mizutani, M., Yamanari, S., Higashi, M., Murata, N., Inoue, M., Yugami, J., Endo, S., Hayashi, T., Yamashita, T., Oda, H., Inoue, Y.
Format: Conference Proceeding
Language:English
Subjects:
Annealing
Atherosclerosis
Capacitive sensors
Degradation
Fabrication
High K dielectric materials
High-K gate dielectrics
Stress
Surface-mount technology
Tin
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Summary:Performance of advanced hybrid-gate CMOS (poly-Si/HfSiON nMIS and poly-Si/TiN/HfSiON pMIS) is demonstrated. V th of pMIS is controlled by fluorine implantation and by PVD/CVD-stacked TiN, which has higher WF than conventional single-CVD TiN. This combination enables sufficient V th -control without degradation of device characteristics by excessive fluorine. Performance boosters such as strain enhancement techniques and laser annealing are easily and successfully introduced, and high current drivability is obtained. This advanced hybrid structure is promising for CMIS platforms of 45-nm node and beyond.
ISSN:0743-1562
DOI:10.1109/VLSIT.2007.4339697