Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel r...

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Main Authors: Eiho, A., Sanuki, T., Morifuji, E., Iwamoto, T., Sudo, G., Fukasaku, K., Ota, K., Sawada, T., Fuji, O., Nii, H., Togo, M., Ohno, K., Yoshida, K., Tsuda, H., Ito, T., Shiozaki, Y., Fuji, N., Yamazaki, H., Nakazawa, M., Iwasa, S., Muramatsu, S., Nagaoka, K., Iwai, M., Ikeda, M., Saito, M., Naruse, H., Enomoto, Y., Kitano, Yamada, S., Imai, K., Nagashima, N., Kuwata, T., Matsuoka, F.
Format: Conference Proceeding
Language:English
Subjects:
Capacitive sensors
CMOS technology
Energy management
Gate leakage
Germanium silicon alloys
Grain size
Silicon germanium
Substrates
Surface-mount technology
Tensile stress
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Summary:The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule (190 nm) in 45 nm technology node.
ISSN:0743-1562
DOI:10.1109/VLSIT.2007.4339699