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Management of Power and Performance with Stress Memorization Technique for 45nm CMOS
The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel r...
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| creator | Eiho, A. Sanuki, T. Morifuji, E. Iwamoto, T. Sudo, G. Fukasaku, K. Ota, K. Sawada, T. Fuji, O. Nii, H. Togo, M. Ohno, K. Yoshida, K. Tsuda, H. Ito, T. Shiozaki, Y. Fuji, N. Yamazaki, H. Nakazawa, M. Iwasa, S. Muramatsu, S. Nagaoka, K. Iwai, M. Ikeda, M. Saito, M. Naruse, H. Enomoto, Y. Kitano Yamada, S. Imai, K. Nagashima, N. Kuwata, T. Matsuoka, F. |
| description | The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule (190 nm) in 45 nm technology node. |
| doi_str_mv | 10.1109/VLSIT.2007.4339699 |
| format | conference_proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0743-1562 |
| ispartof | 2007 IEEE Symposium on VLSI Technology, 2007, p.218-219 |
| issn | 0743-1562 |
| language | eng |
| recordid | cdi_ieee_primary_4339699 |
| source | IEEE Xplore All Conference Series |
| subjects | Capacitive sensors CMOS technology Energy management Gate leakage Germanium silicon alloys Grain size Silicon germanium Substrates Surface-mount technology Tensile stress |
| title | Management of Power and Performance with Stress Memorization Technique for 45nm CMOS |
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