Algorithms for Modeling a Class of Single Timing Faults in Communication Protocols

A set of graph augmentation algorithms is introduced to model a class of timing faults in timed-EFSM models. It is shown that the test sequences generated based on our models can detect 1 -clock and n -clock timing faults and incorrect timer setting faults in an implementation under test (IUT). It i...

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Bibliographic Details
Published in:IEEE transactions on computers 2008-02, Vol.57 (2), p.274-288
Main Authors: Uyar, M.U., Batth, S.S., Yu Wang, Fecko, M.A.
Format: Article
Language:English
Subjects:
Algorithms
Augmentation
Automata
Classification algorithms
Clocks
Computational modeling
Computer simulation
Conformance Testing
Extended Finite State Machine (EFSM)
Fault Modeling
Faults
Finite State Machine (FSM)
Graphs
Protocols
Real time systems
Specifications
Testing
Time measurements
Timed EFSM
Timers
Timing
Timing devices
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Description
Summary:A set of graph augmentation algorithms is introduced to model a class of timing faults in timed-EFSM models. It is shown that the test sequences generated based on our models can detect 1 -clock and n -clock timing faults and incorrect timer setting faults in an implementation under test (IUT). It is proven that the size of the augmented graph resulting from our augmentation algorithms is on the same order of magnitude as that of the original specification.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2007.70772