Bringing NoCs to 65 nm

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The experimental results from fully working 65-nm N...

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Bibliographic Details
Published in:IEEE MICRO 2007-09, Vol.27 (5), p.75-85
Main Authors: Pullini, A., Angiolini, F., Murali, S., Atienza, D., De Micheli, G., Benini, L.
Format: Article
Language:English
Subjects:
Analysis
Bandwidth
Bridges
Buses (vehicles)
Chips
CMOS
Construction
Crosstalk
deep submicron design
design aids
Design engineering
Experiments
low-power design
multicore architectures
network on chip
Network operating systems
Network topology
Network-on-a-chip
Networks
on-chip interconnection networks
power management
Propagation delay
Protocols
Scalability
Sheds
Switches
Topology
Wires
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Description
Summary:Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The experimental results from fully working 65-nm NoC designs and a detailed scalability analysis are presented. The network on chip (NoC) is a promising solution to the scalability problem. NoCs build upon improvements in bus architecture-for example, in terms of topology design.
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2007.4378785